`timescale 1ns/1ns

module sdram_tb(

	//////////// CLOCK //////////

	//////////// SDRAM //////////
	output		    [12:0]		DRAM_ADDR,
	output		     [1:0]		DRAM_BA,
	output		          		DRAM_CAS_N,
	output		          		DRAM_CKE,
	output		          		DRAM_CLK,
	output		          		DRAM_CS_N,
	inout 		    [15:0]		DRAM_DQ,
	output		          		DRAM_LDQM,
	output		          		DRAM_RAS_N,
	output		          		DRAM_UDQM,
	output		          		DRAM_WE_N

);
reg clk_c0;
reg clk_c1;

wire [24:0] ADDRESS;// = 25'd0; {BA,行，列}

reg reset_DRAM_CTRL;
reg [15:0] DATA_WRITE;
wire [15:0] DATA_READ;

reg [24:0] ADDR_COUNTER_WRITE = 25'd0;
reg [24:0] ADDR_COUNTER_READ=25'd0;

reg write_pulse=1'b0;
reg read_pulse=1'b0;



initial begin
	clk_c0<=1;
	reset_DRAM_CTRL<=0;
    //#3;
    //clk_c1<=1;
	#100;
	reset_DRAM_CTRL<=1;
end

always #5 clk_c0=~clk_c0;
always @clk_c0 #3 clk_c1=clk_c0;

initial begin
	#101000;
    #10 write_pulse=1;
    #10 DATA_WRITE=16'd8;
    #20 ;//nop
	#10 ADDR_COUNTER_WRITE=ADDR_COUNTER_WRITE+1; 
        DATA_WRITE=16'd1;
    #20
    #10 ADDR_COUNTER_WRITE=ADDR_COUNTER_WRITE+1;
        write_pulse=0;
    #200 read_pulse=1;
    #40; 
    #10 ADDR_COUNTER_READ=ADDR_COUNTER_READ+1;
    #40;
    #10 read_pulse=0;
    
    
end

initial begin
    #63300000   read_pulse=1;
    #700000     read_pulse=0;
end

assign ADDRESS=(write_pulse==1)?ADDR_COUNTER_WRITE:ADDR_COUNTER_READ;


sdram_controller sdram_controller_inst(
			.RE(read_pulse),
			.WR(write_pulse),
			.ADDR(ADDRESS),//in 24:0
			.RD_REQUEST_APPROVED(RD_REQUEST_APPROVED),//out
			.WR_REQUEST_APPROVED(WR_REQUEST_APPROVED),
	  		.RD_DATA(DATA_READ),//out 15:0
			.WR_DATA(DATA_WRITE),//out 15:0
			.MAX10_CLK1_100(clk_c0),
	 		.MAX10_CLK2_100_3ns(clk_c1),
			.DRAM_ADDR(DRAM_ADDR),
		   .DRAM_BA(DRAM_BA),
		   .DRAM_CAS_N(DRAM_CAS_N),
		   .DRAM_CKE(DRAM_CKE),
		   .DRAM_CLK(DRAM_CLK),
	      .DRAM_CS_N(DRAM_CS_N),
			.DRAM_DQ(DRAM_DQ),
	      .DRAM_LDQM(DRAM_LDQM),
	      .DRAM_RAS_N(DRAM_RAS_N),
	      .DRAM_UDQM(DRAM_UDQM),
	      .DRAM_WE_N(DRAM_WE_N),
			.reset_n(reset_DRAM_CTRL));
            
sdram_model_plus sdram_model_plus_inst(
	.Dq(DRAM_DQ),
	.Addr(DRAM_ADDR),
	.Ba(DRAM_BA), 
	.Clk(DRAM_CLK), 
	.Cke(DRAM_CKE ), 
	.Cs_n(DRAM_CS_N), 
	.Ras_n(DRAM_RAS_N), 
	.Cas_n(DRAM_CAS_N), 
	.We_n(DRAM_WE_N), 
	.Dqm({DRAM_UDQM,DRAM_LDQM}),
	.Debug(1'b1)
);
endmodule